


module bus_timer(
    input clk , 
    input rst_n , 

    input  wire [7:0]  m_dat_i  , 
    output wire [7:0]  m_dat_o  , 
    input  wire [7:0]  m_adr_i  , 
    input  wire        m_wen_i  

) ;


always @(posedge clk ) begin
    if(~rst_n) begin

    end else begin
        if(m_wen_i) begin
            case(m_adr_i)
                8'h00: begin 

                    $display("%t ns | timer=%d" , $time , m_dat_i) ;
                end 
            endcase 
        end
    end
end


endmodule 

